Inside Replay Essentials.txt

Inside_Replay_Essentials.txt is a rewritten version of the original documentation and is used during development of the RR ROM (enduser edition) only. The FlashMode e.g. is not described at all. Side effects are explained nevertheless.

This document explains in short the register setup of the Retro Replay original
cartridge in non-flash mode. Since other ROM banking setups rather than the ones
we use as an "environment" for the RR code are possible the document may lack or
appear biased. Please comment!

The entry to the ROM is the bank 0 reset vector ($8000 -> CBM80) just like on AR
hardware. (TODO: Check Atomic and Nordic out of curiosity)
On RR hardware we _SHOULD_ initialise Bit 1, 2 and 6 of $DE01 to enable
the REU compatible memory mode, keep the freeze button working and disallow banking
of cart RAM other than from bank 0.

As a result any clone hardware emulating AR and RR hardware "seperately" in some
way should by default select to enable any accessory connector and of course the
REU compatible memory map. Clone devices such as the 1541u may choose to "ignore"
write accesses $de01 rendering it to a non-register effectively.
We hereby swear we will not use $de01 for setting reading back the current ROM bank!
(Note: $de01 is currently used for SilverSurfer detection but that needs fixing anyhow.)

Therefore $de01 can safely be ignored on hardware implementations of the register
setup as described below.

Of course any address on the IO1 page at $deXX not being used by the control
registers of either the cartridge, SilverSurfer or RR-Net needs to map to the
internal cartridge RAM - not to the C64 RAM. This should be obvious though.

All of the above will additionally allow distinguishing between real RR hardware
and clones since simply reading back our initialisation value from startup from
RAM bank 0 of the cartridge should reveal wether the $de01 register is available
or not.

There are side effects of course: Dropping the "AllowBank" bit on clone hardware
adds a little incompatibility but at least the RR team never found it to be a useful
feature. (Check with Graham required)
RAM AllowBank usage would fragment RAM on banks 2 and above and in regards of using
it continously for e.g. storing source codes and alike it would be a bad idea to use.



This leaves us with just one register at $de00 set to $00 on reset/powerup
which works like this on WRITE:

bit 7 - ROM bank selector (A15)
bit 6 - Restores memory map after freeze, GAME and EXROM "reset"
      - no function when not in freeze mode
bit 5 - 0 = ROM and 1 = RAM
bit 4 - ROM bank selector (A14)
bit 3 - ROM bank selector (A13)
bit 2 - 1 = cartridge kill
bit 1 - 1 = /EXROM high  (0 = "assert" and 1 = "de-assert")
bit 0 - 1 = /GAME  low   (1 = "assert" and 0 = "de-assert")


Reading $de00 should result in:
bit 7 - ROM bank selector (A15)
bit 6 - initialised with 1 by RR software (REU compat memory map)
      - clones should always return 1
bit 5 - 0 since no flash 
      - clones should always return 1
bit 4 - ROM bank selector (A14)
bit 3 - ROM bank selector (A13)
bit 2 - 1 when freeze button is pressed and 0 otherwise
bit 1 - initialised with 0 by RR software (AllowBank)
      - clones should always return 0
bit 0 - 0 = no flash


List me: ROM can be mapped to $8000, $a000 or $e000 with the corresponding
status on GAME and EXROM.

On freeze bank 0 is activated at $e000 so the NMI of bank 0 is leading the
freeze code further. Make sure to pass by the return code which on current
RR needs to be aligned to a kernel RTS. :)

During freeze mode the RR hardware is keeping control over GAME and EXROM and
ignores any write accesses until bit 6 is set. On setting bit 6 of $de00 the
standard memory map will instantly be restored and GAME/EXROM can be used again.

Freeze mode allows ROM banks to be mapped by $de00 as before but of course they
are mapped to $e000. RAM can only be on the free IO1 area. 



Last words for the easy minded - the ultimate weapon against a freezer is the
perfectly aligned stack pointer! :)
Code cannot be frozen properly whenever the stack does not at least have XXX
(TODO: add numbers from several carts here) bytes left for storing stuff during
the switch from Ultimax to sanity.

Please ignore the text below - need it for some testing:

The Freezer is essentially made up of two RS-Flipflops, as with all freezer- cartridges. However, the Retro Replay has much more sophisticated conditions for setting and resetting them. Let's call the two Flipflops "Freeze Pending" and "Freeze done". Both are reset on a hardware reset. Holding the Freeze button down for more than two microseconds and then releasing it will set the "Freeze Pending" Flipflop. At the same time, the IRQ and NMI lines are asserted, and the CPU supervision logic is started: This logic waits for the CPU to do the necessary write-accesses to stack: Before the 6510 serves an IRQ or an NMI, the program pointer and the processor status are saved on the stack ($0100 to $01ff). These three consecutive write cycles give a clear indication that the CPU will fetch the IRQ/NMI vector in the next cycle, so this is the set-condition for the "Freeze Done" Flipflop. Setting FreezeDone resets FreezePending, and disables the Freeze button. Further, the "Freeze" memory map is set, replacing the original C-64 Kernal IRQ/NMI with the vectors of the Retro Replay cartridge.

Even if the IRQ is served "late" - the CPU supervision circuit is patient. It can wait forever, and let the computer run without affecting the memory map. If the program you are trying to freeze has disabled all IRQs and NMIs, the Freeze button will simply have no effect. The FreezeDone Flipflop is reset by setting bit 6 of the $de00 register, activating the standard memory map of the cartridge.